digital electronics free text book pdf by Steven T. Karris || best digital electronics book ||

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electronics is major part in day-to-day life., learning of electronics is very important in now a days. electronics makes life style easier.
electronics having huge future and opportunities.

Electronics divided into two parts,
1. Digital Electronics
2. Analog Electronics.

here we are providing The most famous text book for digital electronics with high standards.

Contents in  digital electronics free text book pdf by Steven T. Karris text book :

1 Common Number Systems and Conversions 

1.1 Decimal, Binary, Octal, and Hexadecimal Systems

1.2 Binary, Octal, and Hexadecimal to Decimal Conversions

1.3 Decimal to Binary, Octal, and Hexadecimal Conversions

1.4 Binary−Octal−Hexadecimal Conversions

1.5 Summary

1.6 Exercises

1.7 Solutions to End−of−Chapter Exercises

2 Operations in Binary, Octal, and Hexadecimal Systems

2.1 Binary System Operations 

2.2 Octal System Operations 

2.3 Hexadecimal System Operations 

2.4 Complements of Numbers 

2.4.1 Tens−Complement 

2.4.2 Nines−Complement 

2.4.3 Twos−Complement 

2.4.4 Ones−Complement 

2.5 Subtraction with Tens− and Twos−Complements 

2.6 Subtraction with Nines− and Ones−Complements

2.7 Summary

2.8 Exercises 

2.9 Solutions to End−of−Chapter Exercises

MATLAB Computations

3 Sign Magnitude and Floating Point Arithmetic 

3.1 Signed Magnitude of Binary Numbers

3.2 Floating Point Arithmetic 

3.2.1 The IEEE Single Precision Floating Point Arithmetic

3.2.2 The IEEE Double Precision Floating Point Arithmetic

3.3 Summary 

3.4 Exercises

3.5 Solutions to End−of−Chapter Exercises

MATLAB Computations

4 Binary Codes 4−1

4.1 Encoding

4.1.1 Binary Coded Decimal (BCD) 

4.1.2 The Excess−3 Code

4.1.3 The 2*421 Code 

4.1.4 The Gray Code 

4.2 The American Standard Code for Information Interchange (ASCII) Code

4.3 The Extended Binary Coded Decimal Interchange Code (EBCDIC) 

4.4 Parity Bits 

4.5 Error Detecting and Correcting Codes

4.6 Cyclic Codes 

4.7 Summary 

4.8 Exercises 

4.9 Solutions to End−of−Chapter Exercises 

5 Fundamentals of Boolean Algebra 

5.1 Basic Logic Operations 

5.2 Fundamentals of Boolean Algebra 

5.2.1 Postulates 

5.2.2 Theorems 

5.3. Truth Tables 

5.4 Summary

5.5 Exercises 

5.6 Solutions to End−of−Chapter Exercises

6 Minterms and Maxterms 

6.1 Minterms

6.2 Maxterms 

6.3 Conversion from One Standard Form to Another

6.4 Properties of Minterms and Maxterms 

6.5 Summary 

6.6 Exercises 

6.7 Solutions to End−of−Chapter Exercises 

7 Combinational Logic Circuits 

7.1 Implementation of Logic Diagrams from Boolean Expressions 

7.2 Obtaining Boolean Expressions from Logic Diagrams 

7.3 Input and Output Waveforms 

7.4 Karnaugh Maps

7.4.1 K−map of Two Variables 

7.4.2 K−map of Three Variables 

7.4.3 K−map of Four Variables 

7.4.4 General Procedures for Using a K−map of n Squares

7.4.5 Don’t Care Conditions 

7.5 Design of Common Logic Circuits

7.5.1 Parity Generators/Checkers

7.5.2 Digital Encoders

7.5.3 Decimal−to−BCD Encoder

7.5.4 Digital Decoders

7.5.5 Equality Comparators

7.5.6 Multiplexers and Demultiplexers

7.5.7 Arithmetic Adder and Subtractor Logic Circuits

7.6 Summary

7.7 Exercises 

7.8 Solutions to End−of−Chapter Exercises

Simulink Modeling

7−56 through 

8 Sequential Logic Circuits

8.1 Introduction to Sequential Circuits 

8.2 Set−Reset (SR) Flip Flop

8.3 Data (D) Flip Flop 

8.4 JK Flip Flop

8.5 Toggle (T) Flip Flop 

8.6 Flip Flop Triggering 

8.7 Edge−Triggered Flip Flops

8.8 Master / Slave Flip Flops 

8.9 Conversion from One Type of Flip Flop to Another 

8.10 Analysis of Synchronous Sequential Circuits 

8.11 Design of Synchronous Counters 

8.12 Registers

8.13 Ring Counters 

8.14 Ring Oscillators 

8.15 Summary 

8.16 Exercises 

8.17 Solutions to End−of−Chapter Exercises 

Simulink Modeling

9 Memory Devices

9.1 Random−Access Memory (RAM)

9.2 Read−Only Memory (ROM) 

9.3 Programmable Read−Only Memory (PROM)

9.4 Erasable Programmable Read−Only Memory (EPROM)

9.5 Electrically−Erasable Programmable Read−Only Memory (EEPROM) 

9.6 Flash Memory

9.7 Memory Sticks 

9.8 Cache Memory

9.9 Virtual Memory

9.10 Scratch Pad Memory

9.11 The Simulink Memory Block 

9.12 Summary 

9.13 Exercises

9.14 Solutions to End−of−Chapter Exercises 

Simulink Modeling

10 Advanced Arithmetic and Logic Operations 

10.1 Computers Defined

10.2 Basic Digital Computer System Organization and Operation 

10.3 Parallel Adder 

10.4 Serial Adder 

10.5 Overflow Conditions 

10.6 High-Speed Addition and Subtraction 

10.7 Binary Multiplication 

10.8 Binary Division 

10.9 Logic Operations of the ALU 

10.10 Other ALU functions 

10.11 Logic and Bit Operations with Simulink Blocks 

10.11.1 The Logical Operator Block 

10.11.2 The Relational Operator Block 

10.11.3 The Interval Test Block 

10.11.4 The Interval Test Dynamic Block

10.11.5 The Combinatorial Logic Block 

10.11.6 The Compare to Zero Block 

10.11.7 The Compare to Constant Block 

10.11.8 The Bit Set Block 

10.11.9 The Clear Bit Block 

10.11.10 The Bitwise Operator Block 

10.11.11 The Shift Arithmetic Block 

10.11.12 The Extract Bits Block 

10.12Summary 

10.13 Exercises

10.14 Solutions to End−of−Chapter Exercises

Simulink Modeling

11 Introduction to Field Programmable Devices 

11.1 Programmable Logic Arrays (PLAs) 

11.2 Programmable Array Logic (PAL) 

11.3 Complex Programmable Logic Devices (CPLDs) 

11.3.1 The Altera MAX 7000 Family of CPLDs 

11.3.2 The AMD Mach Family of CPLDs 

11.3.3 The Lattice Family of CPLDs 

11.3.4 Cypress Flash370 Family of CPLDs 

11.3.5 Xilinx XC9500 Family of CPLDs 

11.3.6 CPLD Applications 

11.4 Field Programmable Gate Arrays (FPGAs)

11.4.1 SRAM−Based FPGA Architecture 

11.4.2 Xilinx FPGAs 

11.4.3 Atmel FPGAs 

11.4.5 Altera FPGAs 

11.4.6 Lattice FPGAs

11.4.7 Antifuse-Based FPGAs 

11.4.8 Actel FPGAs

11.4.8 QuickLogic FPGAs 

11.5 FPGA Block Configuration − Xilinx FPGA Resources 

11.6 The CPLD versus FPGA Trade−Off

11.7 What is Next

11.8 Summary

11.9 Exercises

11.10 Solutions to End−of−Chapter Exercises 

A Introduction to MATLAB® A−1

A.1 Command Window ..............................................................................................A−1

A.2 Roots of Polynomials ............................................................................................A−3

A.3 Polynomial Construction from Known Roots ......................................................A−4

A.4 Evaluation of a Polynomial at Specified Values ...................................................A−5

A.5 Rational Polynomials ............................................................................................A−8

A.6 Using MATLAB to Make Plots ............................................................................A−9

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Copyright © Orchard Publications

A.7 Subplots ..............................................................................................................A−18

A.8 Multiplication, Division and Exponentiation ....................................................A−19

A.9 Script and Function Files ...................................................................................A−26

A.10 Display Formats ..................................................................................................A−31

MATLAB Computations: Entire Appendix A

B Introduction to Simulink® B−1

B.1 Simulink and its Relation to MATLAB ...............................................................B−1

B.2 Simulink Demos ..................................................................................................B−20

Simulink Modeling: Entire Appendix B

C Introduction to ABEL Hardware Description Language C−1

C.1 Introduction .........................................................................................................C−1

C.2 Basic Structure of an ABEL Source File ..............................................................C−1

C.3 Declarations .........................................................................................................C−3

C.4 Numbers ...............................................................................................................C−5

C.5 Directives .............................................................................................................C−6

C.5.1 The @alternate Directive .........................................................................C−6

C.5.2 The @radix Directive ...............................................................................C−7

C.5.3 The @standard Directive ..........................................................................C−7

C.6 Sets ....................................................................................................................C−7

C.6.1 Indexing or Accessing a Set ......................................................................C−8

C.6.2 Set Operations ...........................................................................................C−9

C.7 Operators ............................................................................................................C−11

C.7.1 Logical Operators ....................................................................................C−11

C.7.2 Arithmetic Operators ..............................................................................C−12

C.7.3 Relational Operators ...............................................................................C−12

C.7.4 Assignment Operators .............................................................................C−13

C.7.5 Operator Priorities ...................................................................................C−13

C.8 Logic Description ...............................................................................................C−14

C.8.1 Equations .................................................................................................C−14

C.8.2 Truth Tables ............................................................................................C−15

C.8.3 State Diagram ..........................................................................................C−18

C.8.4 Dot Extensions ........................................................................................C−21

C.9 Test Vectors .......................................................................................................C−22

C.10 Property Statements ...........................................................................................C−23

C.11 Active−Low Declarations ..................................................................................C−23

Digital Circuit Analysis and Design with Simulink ® Modeling vii

and Introduction to CPLDs and FPGAs, Second Edition

Copyright © Orchard Publications

D Introduction to VHDL D−1

D.1 Introduction ..........................................................................................................D−1

D.2 The VHDL Design Approach ..............................................................................D−1

D.3 VHDL as a Programming Language .....................................................................D−3

D.3.1 Elements ..................................................................................................D−3

D.3.2 Comments ................................................................................................D−4

D.3.3 Identifiers .................................................................................................D−4

D.3.4 Literal Numbers .......................................................................................D−4

D.3.5 Literal Characters ....................................................................................D−5

D.3.6 Literal Strings ..........................................................................................D−5

D.3.7 Bit Strings ................................................................................................D−5

D.3.8 Data Types................................................................................................D−5

D.3.9 Integer Types ...........................................................................................D−6

D.3.10 Physical Types .........................................................................................D−7

D.3.11 Floating Point Types ................................................................................D−8

D.3.12 Enumeration Types .................................................................................D−9

D.3.13 Arrays ......................................................................................................D−9

D.3.14 Records ..................................................................................................D−11

D.3.15 Subtypes .................................................................................................D−11

D.3.16 Object Declarations ...............................................................................D−12

D.3.17 Attributes ..............................................................................................D−13

D.3.18 Expressions and Operators ....................................................................D−14

D.3.19 Sequential Statements ...........................................................................D−15

D.3.20 Variable Assignments ............................................................................ D−15

D.3.21 If Statement ...........................................................................................D−16

D.3.22 Case Statement ......................................................................................D−16

D.3.23 Loop Statements ....................................................................................D−17

D.3.24 Null Statement ......................................................................................D−19

D.3.25 Assertions ..............................................................................................D−19

D.3.26 Subprograms and Packages ....................................................................D−20

D.3.27 Procedures and Functions .....................................................................D−20

D.3.28 Overloading ...........................................................................................D−23

D.3.29 Package and Package Body Declarations ..............................................D−24

D.3.30 Package Use and Name Visibility ..........................................................D−26

D.4 Structural Description ........................................................................................D−26

D.4.1 Entity Declarations ................................................................................D−26

D.4.2 Architecture Declarations .....................................................................D−29

D.4.3 Signal Declarations ................................................................................D−30

D.4.4 Blocks .....................................................................................................D−30

D.4.5 Component Declarations ......................................................................D−32

D.4.6 Component Instantiation ......................................................................D−33

viii Digital Circuit Analysis and Design with Simulink ® Modeling

and Introduction to CPLDs and FPGAs, Second Edition

Copyright © Orchard Publications

D.5 Behavioral Description ...................................................................................... D−33

D.5.1 Signal Assignment ................................................................................ D−34

D.5.2 Process and the Wait Statement .......................................................... D−35

D.5.3 Concurrent Signal Assignment Statements ......................................... D−38

D.5.4 Conditional Signal Assignment ............................................................ D−38

D.5.5 Selected Signal Assignment .................................................................. D−40

D.6 Organization ....................................................................................................... D−41

D.6.1 Design Units and Libraries .................................................................... D−41

D.6.2 Configurations ....................................................................................... D−43

D.7 Design Example ................................................................................................. D−47

E Introduction to Verilog E−1

E.1 Description E−1

E.2 Verilog Applications ............................................................................................. E−2

E.3 The Verilog Programming Language .................................................................... E−2

E.4 Lexical Conventions E−6

E.5 Program Structure ................................................................................................. E−7

E.6 Data Types ............................................................................................................ E−9

E.6.1 Physical Data Types ................................................................................... E−9

E.6.2 Abstract Data Types ................................................................................ E−11

E.7 Operators ............................................................................................................ E−11

E.7.1 Binary Arithmetic Operators ................................................................... E−11

E.7.2 Unary Arithmetic Operators ................................................................... E−12

E.7.3 Relational Operators ............................................................................... E−12

E.7.4 Logical Operators .................................................................................... E−12

E.7.5 Bitwise Operators .................................................................................... E−13

E.7.6 Unary Reduction Operators .................................................................... E−13

E.7.7 Other Operators ...................................................................................... E−14

E.7.8 Operator Precedence ............................................................................... E−14

E.8 Control Statements ............................................................................................. E−15

E.8.1 Selection Statements ............................................................................... E−15

E.8.2 Repetition Statements ............................................................................. E−16

E.9 Other Statements ............................................................................................... E−17

E.9.1 Parameter Statements ............................................................................. E−17

E.9.2 Continuous Assignment Statements ....................................................... E−17

E.9.3 Blocking Assignment Statements ............................................................ E−17

E.9.4 Non-Blocking Assignment Statements ................................................... E−18

E.10 System Tasks ....................................................................................................... E−19

E.11 Functions E−21

E.12 Timing Control ................................................................................................... E−22

E.12.1 Delay Control ........................................................................................ E−22

Digital Circuit Analysis and Design with Simulink ® Modeling ix

and Introduction to CPLDs and FPGAs, Second Edition

Copyright © Orchard Publications

E.12.2 Event Control ........................................................................................ E−22

E.12.3 Wait Control ......................................................................................... E−23

E.12.4 Fork and Join Control ........................................................................... E−23

F Introduction to Boundary Scan Architecture F−1

F.1 The IEEE Standard 1149.1 .................................................................................... F−1

F.2 Introduction ...........................................................................................................F−1

F.3 Boundary Scan Applications .................................................................................F−3

F.4 Board with Boundary-Scan Components ..............................................................F−4

F.5 Field Service Boundary-Scan Applications ...........................................................F−5

References R−1

Index IN−1

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